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CY7C375I
UltraLogicTM 128-Macrocell Flash CPLD
Features
* * * * 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable (ISRTM) Flash technology -- JTAG Interface * Bus Hold capabilities on all I/Os and dedicated inputs * No hidden delays * High speed -- fMAX = 125 MHz -- tPD = 10 ns -- tS = 5.5 ns -- tCO = 6.5 ns * Fully PCI compliant * 3.3V or 5.0V I/O operation * Available in 160-pin TQFP, CQFP, and PGA packages
Functional Description
The CY7C375I is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370iTM family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C375I is designed to bring the ease of use and high performance of the 22V10 to high-density PLDs. Like all of the UltraLogicTM FLASH370i devices, the CY7C375I is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins. The ISR interface is enabled using the programming voltage pin (ISR EN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments.
Logic Block Diagram
CLOCK INPUTS INPUTS 1 INPUT MACROCELL 4 4 INPUT/CLOCK MACROCELLS 4 36 PIM 16 36 16 36 16 36 16 LOGIC BLOCK 16 I/Os I/O 112-I/O127
I/O0-I/O15
16 I/Os
LOGIC BLOCK
A
16 I/Os LOGIC BLOCK
36 16 36 16 36 16 36 16
H
LOGIC BLOCK 16 I/Os
I/O 16-I/O31
B
16 I/Os LOGIC BLOCK
G
LOGIC BLOCK 16 I/Os
I/O 96-I/O111
I/O 32-I/O47
C
16 I/Os LOGIC BLOCK
F
LOGIC BLOCK 16 I/Os
I/O 80-I/O95
I/O 48-I/O63
D
64
E
64
I/O 64-I/O79
7C375i-1
Selection Guide
7C375i-125 7C375i-100 7C375i-83 Maximum Propagation Delay , tPD (ns) Minimum Set-Up, tS (ns) Maximum Clock to Output , tCO (ns) Typical Supply Current, ICC (mA)
[1] [1]
7C375iL-83 15 8 8 75
7C375i-66 20 10 10 125
7C375iL-66 20 10 10 75
10 5.5 6.5 125
12 6 7 125
15 8 8 125
Note: 1. The 3.3V I/O mode timing adder, t 3.3IO, must be added to this specification when VCCIO = 3.3V
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 July 1, 1998
CY7C375I
Pin Configurations
Top View TQFP
GND VCCINT ISREN I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 I/O 122 I/O 121 I/O 120 GND I/O 119 I/O 118 I/O 117 VCCIO I/O 15 I/O 14 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 VCCIO I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 GND I/O 13 I/O 12 I/O 11 I/O 10 I/O 9 I/O 8 GND
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 GND I/O16 I/O17 I/O18 I/O19 I/O20 /SCLK I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O110 I/O109 I/O108 /SDI I/O107 I/O106 I/O105 I/O104 GND I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 CLK3 /I4 GND VCCIO CLK2 /I3 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 83 82 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O81 I/O80 GND I/O30 I/O31 CLK0 /I0 VCCIO GND CLK1 /I1 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 VCCIO 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 VCCIO I/O111 I/O52 /SMODE I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I2 VCCIO VCCINT I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 I/O78 I/O79 VCCIO GND GND I/O48 I/O49 I/O50 I/O51
140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
7C375i-2
2
CY7C375I
Pin Configurations (continued)
Top View CQFP
GND VCC ISREN I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 I/O 122 I/O 121 I/O 120 GND I/O 119 I/O 118 I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 GND VCC I/O 15 I/O 14 I/O 13 I/O 12 I/O 11 I/O 10 I/O 9 I/O 8 GND I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 VCC 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
GND I/O16 I/O17 I/O18 I/O19 I/O20 /SCLK I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O110 I/O109 I/O108 /SDI I/O107 I/O106 I/O105 I/O104 GND I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 CLK3 /I4 GND VCC CLK2 /I3 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 83 82 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O81 I/O80 GND I/O30 I/O31 CLK0 /I0 VCC GND CLK1 /I1 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 VCC 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 VCC I/O111
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141
I/O52 /SMODE I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I2 VCC
I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 GND VCC
GND I/O48 I/O49 I/O50 I/O51
I/O78 I/O79 VCC
7C375i-3
3
CY7C375I
Pin Configurations (continued)
PGA Bottom View
R P I/O109 I/O 112 I/O115 I/O118 I/O121 I/O123 I/O126 I/O127 I/O0 I/O3 I/O5 I/O7 I/O10 I/O11 I/O14
I/O106 I/O 110 I/O113 I/O 108 I/O111 /SDI
I/O116
I/O119 I/O122
I/O125
GND
I/O1
I/O4
I/O6
I/O9
I/O13
I/O15 I/O17
I/O16 I/O19
N M
I/O105
I/O114
I/O117 I/O120
I/O124
ISREN
I/O2
GND
I/O8
I/O12
GND
I/O102 I/O 104 I/O107
VCC
VCC
GND
VCC
GND
I/O18
I/O20 /SCLK I/O23
I/O22
L
I/O100 I/O 101 I/O103
I/O21
I/O25
K
I/O98
I/O99
GND CLK3 /I4 CLK2 /I3 I/O92
I/O24
I/O26
I/O27
J
I/O96
I/O97
VCC
VCC
CLK28 CLK 0 /I0 CLK1 /I1 GND
I/O29
I/O30
H
I/O95
GND
GND
GND
GND
I/O31
G
I/O94
I/O93
VCC
VCC
I/O33
I/O32
F
I/O91
I/O90
I/O88
I/O35
I/O34
E
I/O89
I/O87
I/O85
I/O39
I/O37
I/O36
D
I/O86
I/O84
I/O82
GND I/O76 /SDO I/O73
VCC
GND
VCC
VCC
I/O43
I/O40
I/O38
C
I/O83
I/O81
GND
I/O72
GND
I/O66
I2
I/O60
I/O56
I/O53
I/O50
I/O47
I/O44
I/O41
B
I/O80
I/O79
I/O77
I/O70
I/O 68
I/O65
GND
I/O61
I/O58
I/O55
I/O52/ I/O49 SMODE I/O71 12 I/O51 13
I/O46
I/O42
A
I/O78 1
I/O75 2
I/O74 3
I/O71 4
I/O69 5
I/O 67 6
I/O64 7
I/O63 8
I/O62 9
I/O59 10
I/O57 11
I/O48 14
I/O45 15
7C375i-4
Functional Description (continued)
The 128 macrocells in the CY7C375I are divided between eight logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370i architecture are connected with an extremely fast and predictable routing resource--the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. Like all members of the FLASH370i family, the CY7C375I is rich in I/O resources. Every macrocell in the device features an associated I/O pin, resulting in 128 I/O pins on the CY7C375I. In addition, there is one dedicated input and four input/clock pins. Finally, the CY7C375I features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used or the type of application, the timing parameters on the CY7C375I remain the same.
Logic Block The number of logic blocks distinguishes the members of the FLASH370i family. The CY7C375I includes eight logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. Product Term Array The product term array in the FLASH370i logic block includes 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows for very complex functions to be implemented in single passes through the device. Product Term Allocator The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be imple-
4
CY7C375I
mented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370i PLDs. Note that product term allocation is handled by software and is invisible to the user. I/O Macrocell Each of the macrocells on the CY7C375I has a separate I/O pin associated with it. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed, polarity control over the input sum-term, and four global clocks to trigger the register. The macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the eight logic blocks on the CY7C375I to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Programming For an overview of ISR programming, refer to the FLASH370i Family data sheet and for ISR cable and software specifications, refer to ISR data sheets. For a detailed description of ISR capabilities, refer to the Cypress application note, "An Introduction to In System Reprogramming with FLASH370i." PCI Compliance The FLASH370i family of CMOS CPLDs are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The simple and predictable timing model of FLASH370i ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without simple and predictable timing, PCI compliance is dependent upon routing and product term distribution. 3.3V or 5.0V I/O operation The FLASH370i family can be configured to operate in both 3.3V and 5.0V systems. All devices have two sets of VCC pins: one set, VCCINT, for internal operation and input buffers, and another set, V CCIO, for I/O output drivers. VCCINT pins must always be connected to a 5.0V power supply. However, the VCCIO pins may be connected to either a 3.3V or 5.0V power supply, depending on the output requirements. When V CCIO pins are connected to a 5.0V source, the I/O voltage levels are compatible with 5.0V systems. When VCCIO pins are connected to a 3.3V source, the input voltage levels are compatible with both 5.0V and 3.3V systems, while the output voltage levels are compatible with 3.3V systems. There will be an additional timing delay on all output buffers when operating in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is available in commercial and industrial temperature ranges. Bus Hold Capabilities on all I/Os and Dedicated Inputs In addition to ISR capability, a new feature called bus-hold has been added to all FLASH370i I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to V CC or GND. Design Tools Development software for the CY7C371i is available from Cypress's Warp2(R), Warp2SimTM, and Warp3(R) software packages. All of these products are based on the IEEE-standard VHDL language. Cypress also actively supports third-party design tools from companies such as Synopsys, Mentor Graphics, Cadence, and Synario. Please refer to third-party tool support for further information.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State................................................-0.5V to +7.0V DC Input Voltage ............................................-0.5V to +7.0V DC Program Voltage..................................................... 12.5V Output Current into Outputs ........................................ 16 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC VCCINT 5V 0.25V VCCIO 5V 0.25V OR 3.3V 0.3V 5V 0.5V OR 3.3V 0.3V
Industrial
-40C to +85C
5V 0.5V
Military[2]
-55C to +125C
5V 0.5V
Note: 2. TA is the "instant on" case temperature.
5
CY7C375I
Electrical Characteristics Over the Operating Range[3, 4]
Parameter VOH VOHZ VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output HIGH Voltage with Output Disabled[9] Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[8, 9] Power Supply Current[10] VCC = Min. Test Conditions IOH = -3.2 mA (Com'l/Ind)[5] IOH = -2.0 mA (Mil) VCC = Max. IOH = 0 A (Com'l/Ind)[5, 6] IOH = -50 A (Com'l/Ind) VCC = Min. IOL = 12 mA (Mil) Guaranteed Input Logical HIGH voltage for all inputs[7] Guaranteed Input Logical LOW voltage for all inputs VI = Internal GND, VI = VCC VCC = Max., VO = GND or VO = VCC, Output Disabled VCC = Max., VO = 3.3V, Output Disabled[6] VCC = Max., VOUT = 0.5V VCC = Max., IOUT = 0 mA, f = 1 MHz, V IN = GND, VCC VCC = Min., VIL = 0.8V VCC = Min., VIH = 2.0V VCC = Max. VCC = Max. Com'l/Ind. Com'l "L" -66 Military IBHL IBHH IBHLO IBHHO Input Bus Hold LOW Sustaining Current Input Bus Hold HIGH Sustaining Current Input Bus Hold LOW Overdrive Current Input Bus Hold HIGH Overdrive Current +75 -75 +500 -500
[7] [5, 6]
Min. 2.4
Typ.
Max.
Unit V V
4.0 3.6 0.5 2.0 -0.5 -10 -50 0 -30 125 75 125 -70 7.0 0.8 +10 +50 -125 -160 200 125 250
V V V V V V A A A mA mA mA mA A A A A
IOL = 16 mA (Com'l/Ind)[5]
Capacitance[9]
Parameter CI/O[11] CCLK Description Input/Output Capacitance Clock Signal Capacitance Test Conditions VIN = 5.0V at f=1 MHz VIN = 5.0V at f = 1 MHz 5 Min. Max. 8 12 Unit pF pF
Notes: 3. See the last page of this specification for Group A subgroup testing information. 4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT. 5. IOH = -2 mA, IOL = 2 mA for SDO. 6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note "Understanding Bus Hold" for additional information. 7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 9. Tested initially and after any design or process changes that may affect these parameters. 10. Measured with 16-bit counter programmed into each logic block. 11. CI/O for dedicated inputs, and for I/O pins with JTAG functionality is 12 pF,and for the ISREN pin is 15 pF Max.
6
CY7C375I
Inductance[9]
Parameter L Description Maximum Pin Inductance Test Conditions VIN = 5.0V at 5 = 1 MHz 160-Lead TQFP 9 160-Pin CQFP 6 160-Pin CPGA 10 Unit nH
Endurance Characteristics[9]
Parameter N Description Maximum Reprogramming Cycles Test Conditions Normal Programming Conditions Max. 100 Unit Cycles
AC Test Loads and Waveforms
238 (COM'L) 319 (MIL) 5V OUTPUT 35 pF INCLUDING JIG AND (a) SCOPE Equivalent to: 170 (COM'L) 236 (MIL) 5V OUTPUT 5 pF INCLUDING JIG AND (b) SCOPE 170 (COM'L) 236 (MIL) 238 (COM'L) 319 (MIL) 3.0V 90% GND <2ns
7C375i-4 7C375i-5
ALL INPUT PULSES 90% 10% <2ns
10%
THEVENIN EQUIVALENT 99 (COM'L) 136 (MIL) 2.08V(COM'L) OUTPUT 2.13V(MIL)
Parameter[12] tER(-)
VX 1.5V
Output Waveforms--Measurement Level
VOH
0.5V
VX
7C375i-6
tER(+)
2.6V
VOL
tEA(+) 1.5V
0.5V
VX
7c375i-7
VX
tEA(-) Vthe
0.5V
VOH
7c375i-8
VX
0.5V
7c375i-9
VOL
(d) Test Waveforms
Note: 12. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
7
CY7C375I
Switching Characteristics Over the Operating Range[13]
7C375i-125 Parameter tPD tPDL tPDLL tEA tER tWL tWH tIS tIH tICO tICOL Description Input to Combinatorial Output[1] Input to Output Through Transparent Input or Output Latch[1] Input to Output Through Transparent Input and Output Latches[1] Input to Output Enable[1] Input to Output Disable Clock or Latch Enable Input LOW Time[9] Clock or Latch Enable Input HIGH Time Input Register or Latch Set-Up Time Input Register or Latch Hold Time Input Register Clock or Latch Enable to Combinatorial Output[1] Input Register Clock or Latch Enable to Output Through Transparent Output Latch[1] Clock or Latch Enable to Output[1] Set-Up Time from Input to Clock or Latch Enable Register or Latch Data Hold Time Output Clock or Latch Enable to Output Delay (Through Memory Array)[1] Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable Maximum Frequency with Internal Feedback (Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[9] Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO) Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH, Output Data Stable from Output Clock Minus Input Register Hold Time for 7C37x[9, 14] 8 5.5 0 14 10
[9]
7C375i-100 Min. Max. 12 15 16 16 16 3 3 2 2
7C375i-83 7C374iL-83 Min. Max. 15 18 19 19 19 4 4 3 3
7C375i-66 7C375iL-66 Min. Max. 20 22 24 24 24 5 5 4 4 Unit ns ns ns ns ns ns ns ns ns 24 26 ns ns
Min.
Max. 10 13 15 14 14
Combinatorial Mode Parameters
Input Registered/Latched Mode Parameters 3 3 2 2 14 16
16 18
19 21
Ouptut Registered/Latched Mode Parameters tCO tS tH tCO2 tSCS 6.5 6 0 16 12 7 8 0 19 15 8 10 0 24 10 ns ns ns ns ns
tSL
10
12
15
20
ns
tHL
0
0
0
0
ns
fMAX1 fMAX2
125 158.3
100 143
83 125
66 100
MHz MHz
fMAX3
83.3
76.9
62.5
50
MHz
tOH-tIH 37x
0
0
0
0
ns
Notes: 13. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 14. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C375I. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.
8
CY7C375I
Switching Characteristics Over the Operating Range[13] (continued)
7C375i-125 Parameter tICS fMAX4 Description Input Register Clock to Output Register Clock Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) Asynchronous Reset Width[9] Asynchronous Reset Recovery Time[9] Asynchronous Reset to Output Asynchronous Preset Width[9] Asynchronous Preset Recovery Time Asynchronous Preset to Output[1] Tap Controller Frequency 3.3V I/O mode timing adder 500 1
[9] [1]
7C375i-100 Min. 10 100 Max.
7C375i-83 7C374iL-83 Min. 12 83.3 Max.
7C375i-66 7C375iL-66 Min. 15 66.6 Max. Unit ns MHz
Min. 8 125
Max.
Pipelined Mode Parameters
Reset/Preset Parameters tRW tRR tRO tPW tPR tPO fTAP t3.3IO 10 12 16 10 12 16 500 1 12 14 18 500 1 12 14 18 15 17 21 500 1 15 17 21 20 22 26 20 22 26 ns ns ns ns ns ns kHz ns
Tap Controller Parameter 3.3V I/O Mode Parameters
Switching Waveforms
Combinatorial Output
INPUT tPD COMBINATORIAL OUTPUT
7C375i-10
Registered Output
INPUT tS CLOCK tCO REGISTERED OUTPUT tH
tWH CLOCK
tWL
7C375i-11
9
CY7C375I
Switching Waveforms (continued)
Latched Output
INPUT tS LATCH ENABLE tPDL LATCHED OUTPUT
7C375i-12
tH
tCO
Registered Input
REGISTERED INPUT tIS INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tIH
tWH CLOCK
tWL
7C375i-13
Clock to Clock
REGISTERED INPUT
INPUT REGISTER CLOCK tICS OUTPUT REGISTER CLOCK
7C375i-14
tSCS
10
CY7C375I
Switching Waveforms (continued)
Latched Input
LATCHED INPUT tIS LATCH ENABLE tPDL COMBINATORIAL OUTPUT tICO tIH
tWH LATCH ENABLE
tWL
7C375i-15
Latched Input and Output
LATCHED INPUT
tPDLL LATCHED OUTPUT tICOL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tSL tHL
tWH LATCH ENABLE
tWL
7C375i-16
11
CY7C375I
Switching Waveforms (continued)
Asynchronous Reset
tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK
7C375i-17
Asynchronous Preset
tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK
7C375i-18
Output Enable/Disable
INPUT tER OUTPUTS
7C375i-20
tEA
12
CY7C375I
Ordering Information
Speed (MHz) 125 100 83 Ordering Code CY7C375I-125AC CY7C375I-100AC CY7C375I-100AI CY7C375I-83AC CY7C375I-83AI CY7C375I-83GMB CY7C375I-83UMB CY7C375IL-83AC 66 CY7C375I-66AC CY7C375I-66AI CY7C375I-66GMB CY7C375I-66UMB CY7C375IL-66AC Package Name A160 A160 A160 A160 A160 G160 U162 A160 A160 A160 G160 U162 A160 Package Type 160-Lead Thin Quad Flatpack 160-Lead Thin Quad Flatpack 160-Lead Thin Quad Flatpack 160-Lead Thin Quad Flatpack 160-Lead Thin Quad Flatpack 160-Pin Grid Array 160-Pin Ceramic Quad Flatpack[15] 160-Lead Thin Quad Flatpack 160-Lead Thin Quad Flatpack 160-Lead Thin Quad Flatpack 160-Pin Grid Array 160-Pin Ceramic Quad Flatpack 160-Lead Thin Quad Flatpack
[15]
Operating Range Commercial Commercial Industrial Commercial Industrial Military Commercial Commercial Industrial Military Commercial
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 tPD tCO tICO tS tH tIS tIH tICS
Switching Characteristics
Parameter Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
Note: 15. Standard product ships trim and formed in a carrier. This product is also available in a molded carrier ring. Contact local Cypress office for package information.
Document #: 38-00494-F ISR, UltraLogic, FLASH370, FLASH370i, and Warp2Sim are trademarks of Cypress Semiconductor Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
13
CY7C375I
Package Diagrams
160-Pin Thin Plastic Quad Flat Pack (TQFP) A160
51-85049-A
14
CY7C375I
Package Diagrams (continued)
160-Pin PGA G160
15
CY7C375I
Package Diagrams (continued)
160-Lead Ceramic Quad Flatpack (Cavity Up) U162
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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